1. Field of the Invention
The present invention relates to a bootstrap driver, comprising a power output stage for supplying a load in a full-bridge or half-bridge configuration.
2. Description of the Related Art
It is used, in particular, in the field of class-D vertical deflection amplifiers involving BCD (bipolar/CMOS/DMOS) technology, which are intended for screens such as CRTs (cathode-ray tubes), computer monitors or television screens, as well as in full-bridge or half-bridge bootstrap systems.
The diagram in FIG. 1 illustrates the working principle of an example of a power output stage, which is suitable for a half-bridge supply.
This output stage 30 comprises a high-side transistor MHS and a low-side transistor MLS, which are arranged in series between a positive supply terminal 1, to which a positive potential +Vcc is applied, and a negative supply terminal 2, to which a negative potential −Vcc is applied. In BCD technology, the transistors MHS and MLS are for example VDMOS (vertical double-diffused metal-oxide semiconductor) or LDMOS (lateral double-diffused metal-oxide semiconductor) transistors. The voltages referred to below are expressed in relation to the potential −Vcc.
For reasons of current compatibility, the transistors MHS and MLS are generally both N-type transistors, for example NPN bipolar transistors, or N-type MOS transistors (NMOS transistors) as in the example which is represented. In this case, the source of the transistor MHS and the drain of the transistor MLS are connected together, this common node between them forming an output node OUT of the drive circuit, which delivers an output voltage Vout. The drain of the transistor MHS is connected to the terminal 1 and the source of the transistor MLS is connected to the terminal 2.
The output OUT switches between a low state and a high state, corresponding respectively to potentials −Vcc and +Vcc at this node. In order to switch in this way, the potential at the control gate of transistor MHS must become about 10 V higher than the potential at its source (VGs≈10V) when the output OUT changes from the low state to the high state. It therefore needs to become higher than the potential +Vcc. It is conventional to use the bootstrapping technique for this.
The principle of this technique will be explained below with reference to the diagram in FIG. 2, which illustrates an example of a bootstrap driver.
In addition to the output stage 30 with the transistors MHS and MLS, which are NMOS transistors in this case, the driver comprises a voltage regulator 3 arranged between the terminal 2 and a regulated-voltage node A. The regulator 3 delivers a regulated voltage Vreg from which control voltages are obtained, these being applied to the control gates of the transistors MHS and MLS. For this purpose, the driver also comprises a high-side control circuit HSD (standing for “high-side driver”) for controlling the transistor MHS, and low-side control circuit LSD (standing for “low-side driver”) for controlling the transistor MLS. These circuits are inverting stages in the example which is represented.
The circuit LSD is supplied between the voltages −Vcc and Vreg, and receives a control signal X. The circuit HSD is supplied between the voltages Vout and Vboot, where the Vout is the voltage at the output terminal OUT and Vboot is a voltage corresponding substantially to the voltage Vout boosted by the voltage Vreg, and it receives a control signal {overscore (X)} which is the logical inverse of the signal X. The voltage Vreg is available at the node A. The voltage Vboot is available at the boost-voltage node B. In order to generate the voltage Vboot, the driver also comprises a bootstrap diode Dboot, which is connected by its anode to the node A and by its cathode to the node B, as well as a so-called bootstrap capacitance Cboot connected between the node B and the output node OUT.
The bootstrap driver operates in the following way. When the transistor MLS is on (X=0), that is to say when the output node OUT is in the low state (potential −Vcc), the capacitance Cboot becomes charged to a voltage V such that V=Vreg−Vd, where Vd denotes the forward voltage drop of the diode Dboot. When the transistor MHS is turned on ({overscore (X)}=0), the diode Dboot conducts some of the current necessary for charging the gate of the transistor MHS while the output node OUT is still at the potential −Vcc, the rest of this current being obtained later by discharging the capacitance Cboot. The diode Dboot then stores charges. The charge Q accumulated in this way by the diode Dboot is such that Q=Ī×T, where Ī denotes the aforementioned part of the current and where T denotes the recovery time of the diode Dboot. For example, if Ī=100 mA and T=50 ns, then Q=5 nC. In order to turn the diode Dboot off within a specific time tB, when the voltage Vout is increasing towards +Vcc so that the voltage Vout at the output node OUT exhibits a variation
            ⅆ      Vout              ⅆ      t        ,it is therefore necessary for the diode to conduct a reverse current Īrev such that
            I      _        rev    =            I      _        ×                  τ                  t          B                    .      The reverse current Īrev then flows via the anode of the diode Dboot to the node A. An overvoltage will then be produced at the node A if no low-impedance path is available to the reverse current Īrev, especially if the regulator cannot absorb this current.
One drawback is that this overvoltage risks damaging or destroying the regulator 3 as well as the control circuit LSD. This situation is exacerbated when the regulated-voltage Vreg delivered by the regulator 3 is also the supply voltage for logic circuits of the system. This is because the node A is then connected to the supply inputs of these logic circuits, so that the overvoltage which occurs at the node also risks damaging or destroying them.
In order to overcome this drawback, a capacitance may be provided for decoupling this regulator 3, so as to provide a low-impedance path leading to the negative supply terminal 2. In view of the current values involved, however, this decoupling capacitance needs to have a relatively high value (substantially equal to 100 nF). Returning to the example given above, the overvoltage across the terminals of a 100 nF decoupling capacitance is only
            5      ⁢                          ⁢      nC              100      ⁢                          ⁢      nF        =      50    ⁢                  ⁢          mV      .      Such a capacitance nevertheless has to be produced in the form of an external capacitance, which is detrimental in certain applications.
It is also conceivable to provide a switch controlled by suitable logic, in order to short-circuit the regulator at the moment when the voltage variation
      ⅆ    Vout        ⅆ    t  appears at the output OUT, and when the overvoltage consequently risks being produced. This logic must arrange for the switch not to trigger too early or too late in relation to the start of the voltage variation
            ⅆ      Vout              ⅆ      t        .Such logic is consequently quite difficult to produce.